Jonathan A. Titus

Microcomputer Pioneer

Home Jon Titus Mark-8 Lessons Timeline Links Comm Board About

Lesson 10: Interrupt handling on the SX-28

Interrupt Handling
Even considering that the main programming of the SX-28 processor is done with the sequential architecture, SISD, every once and a while its still important to have the concepts of interrupt handling readily available. An interrupt to the processor is a means to which a task or event can take the immediate attention of the processor. Basically, the processor stops all tasks and immediately executes the code located at a special location known as the Interrupt Vector. Once this Interrupt Vector code has completed, the processor returns to the code where the processor left off before the Interrupt Vector was run.

In reality, several things must occur in addition to the aforementioned to ensure proper operation of the interrupt and the rest of the program. For one thing, consider the likely possibility that the interrupt occurred when the W register held a number the main program was using for a calculation. More than likely, the interrupt service routine will use the W register for its purposes too. When the processor finishes the interrupt service routine and returns to what it was doing before, the W register will hold a different value than what it held before the interrupt occurred. This can lead to bizarre program execution. In addition to the W register, the Status and FSR registers must be ‘preserved’ across an interrupt. Traditionally, these issues were dealt with by software within the interrupt service routine.

The Specifics
When an interrupt occurs in an SX chip, the PC, STATUS, FSR, and W registers are saved in special shadow locations, and additional interrupts ignored. The program counter is loaded with $00, (The Interrupt Vector), and the top three bits of the STATUS register, (PA2:PA0) are cleared to $0. When the interrupt service routine has completed and the ‘RETI’ instruction is executed, the PC, STATUS, FSR, and W registers are restored and the interrupt is re-enabled. Since all of this is automatic, the interrupt service routine does not waste any clock cycles copying several registers back and forth.